发明名称 LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a layout method for a semiconductor integrated circuit, in which wiring to be connected with an input/output terminal of a circuit block and wiring passing on the circuit block and in the vicinity of the circuit block becomes unwired and short-circuited wiring is prevented. SOLUTION: Occurrence of unwiring and the short-circuited wiring is prevented by preventing continuous and adjacent arrangement or circuit blocks with high terminal density by selecting circuit blocks to be arranged adjacently to the circuit blocks with high terminal density from circuit blocks with relatively low terminal density of which arrangement order from the high terminal density blocks is within set order, adjacently arranging them and providing a space where a via can be arranged by making average terminal density of a group of circuit blocks adjacent to the high terminal density blocks to be equal to or less than a permitted standard.
申请公布号 JP2003099492(A) 申请公布日期 2003.04.04
申请号 JP20010291684 申请日期 2001.09.25
申请人 NEC MICROSYSTEMS LTD 发明人 TANAKA MIKITO
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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