发明名称 Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function
摘要 Binary bit addresses for error detection designating the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit. For each digit of the binary bit addresses, first parity codes including a parity code of-data corresponding to all the binary bit addresses having "0" in the digit and a parity code of data corresponding to all-the binary bit addresses having "1" in the digit are generated for both write data and read data. The presence of a memory cell storing erroneous data in both bits is detected when all the first parity codes of the read data are different from the first parity codes of the write data. Thus, the multilevel cell memory can perform reliable error detection/correction by a simple method.
申请公布号 US2003061560(A1) 申请公布日期 2003.03.27
申请号 US20020146074 申请日期 2002.05.16
申请人 FUJITSU LIMITED 发明人 FURUKAWA HIDEYUKI
分类号 G06F11/10;G11C11/56;H03M13/11;(IPC1-7):G11C29/00;H03M13/00 主分类号 G06F11/10
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