| 摘要 |
A receiver for CDMA enables a reduction in a circuit scale including a matched filter and lessening of loads stemming from despread processing. A speed conversion section 10 down-samples a received signal which has been over-sampled at a ratio of four times a chip rate, whereby a matched filter 20 is operated at a two-times oversampling ratio, thereby detecting a path timing. The detected path timing is sent to timing adjustment sections 60 of fingers 30. On the basis of a difference value computed by the DLLs 40, the path timing is corrected, thereby producing a demodulation timing. At the time of correction operation, the path timing is shifted so as to advance or lag by an amount corresponding to one clock cycle of a four-times oversampling frequency. <IMAGE>
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