system for distributing clock sinal with a rise rate such that sinals appearing at first and second output terminals have substantially no signal skew

摘要

The present invention provides a method and apparatus, for integrated circuits, that is able to generate clock signals at different destination points with little or no clock signal delay or skew. A slow rising input clock signal is propagated across a low loss transmission line. The slow rising input signal creates a region of substantially no clock signal delay between the signal at the beginning of the low loss transmission line and the signal at the end of the low loss transmission line. Comparators are used to compare the signals at the beginning and end of the low loss transmission lines and compare them to a reference signal. The compared signals are sampled during the region of substantially no clock signal delay or skew. The sampled clock signals with substantially no delay are sent to local destination points or other low loss transmission lines within the integrated circuit to transmit the signal to remote destination points.