Buffered redundancy circuits for integrated circuit memory devices

摘要

Integrated circuit memory device redundancy circuits are provided that include a plurality of transistors and fuses, a respective transistor and a respective fuse being serially coupled between a respective address line input and a logic circuit to generate a selection signal for a redundant memory cell in response to a predetermined address on the address bus of the integrated circuit memory device. In one embodiment, a decoder is coupled between the address bus of the integrated circuit memory device and a plurality of external address inputs of the integrated circuit memory device. A redundancy enable control circuit may be provided that includes a main fuse and that generates a fuse enable signal in response to opening of the main fuse wherein the plurality of transistors are responsive to the fuse enable signal.