发明名称 |
Partitioned cache memory with switchable access paths |
摘要 |
An information processing device includes a central processing unit, a cache memory unit and first and second decision circuits. The first decision circuit identifies one of partitioned address areas to be accessed before the central processing unit accesses the cache memory unit. The second decision circuit determines whether the above one of the partitioned address areas is a cachable area or a non-cachable area before address tag data is referred to in the cache memory unit.
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申请公布号 |
US6535960(B1) |
申请公布日期 |
2003.03.18 |
申请号 |
US19980074317 |
申请日期 |
1998.05.08 |
申请人 |
FUJITSU LIMITED |
发明人 |
NISHIDA SYUJI;SUETAKE SEIJI;KAMIJO SHUNSUKE;FURUYA KENJI |
分类号 |
G06F12/08;(IPC1-7):G06F12/06 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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