发明名称 Integrated circuit design apparatus, method and program
摘要 An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.
申请公布号 US2003046646(A1) 申请公布日期 2003.03.06
申请号 US20020103895 申请日期 2002.03.25
申请人 FUJITSU LIMITED 发明人 AMANO YASUO;SEKI HIROSHI;MAKINO YUKIO;YAMANISHI YUMIKO;NAKANISHI YOSHIKO;ISHIKAWA YOICHIRO
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F9/45 主分类号 G06F17/50
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