发明名称
摘要 An integrated circuit system having integrated thereon, one or more time vernier subsystems (106,108,110) for fine tuning coarse timing edges of corresponding input signals (103). The system comprises means for generating a control signal for each input signal (103) to specify the amount of fine tuning, and at least one time vernier subsystem having a first input to receive the control signal (112) and a second input to receive a corresponding input signal (103), and means for fine tuning the coarse edges of the corresponding input signal according to the specified amount of fine tuning and for outputting the result. <IMAGE>
申请公布号 JP3382647(B2) 申请公布日期 2003.03.04
申请号 JP19920315904 申请日期 1992.10.30
申请人 发明人
分类号 H03M1/08;G01R31/28;G01R31/319;H03H11/26;H03K5/00;H03K5/13;H03K5/135;H03M1/68;H03M1/74 主分类号 H03M1/08
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