发明名称 DELAY ADJUSTMENT CIRCUIT, TRANSMISSION CIRCUIT, STORAGE DEVICE, AND INFORMATION PROCESSOR
摘要 <p>PROBLEM TO BE SOLVED: To solve the problems, in a conventional system of the device becoming large-scaled in the case of performing delay adjustment for a plurality of transmission paths, and its being unable to conduct delay adjustment at a high speed, when performing the delay adjustment for a plurality of transmission paths. SOLUTION: This system has a data output register 101 in an LSI 10, inputs the output signals to delay circuits 102a, 102b, 102c, and 102d, selects each delay circuit by selecting circuit 103, and sends out data signals 20 to LSIs a11, b12, c13, and d14. The delay adjustment values of the delay circuits a102a, b102b, c102c, and d102d can be changed each by delay adjustment signals. LSI a11, LSI b12, LSI c13, and LSI d14 have a data input register a11, a data input register b112, a data input register c113, and a data input register d114, respectively, and only when LSI selection signals a21, b22, c23, and d24 become effective, do they receive data signals 200.</p>
申请公布号 JP2003060488(A) 申请公布日期 2003.02.28
申请号 JP20010248170 申请日期 2001.08.17
申请人 NEC COMPUTERTECHNO LTD 发明人 OGURA TAKAHIRO
分类号 H03K5/14;(IPC1-7):H03K5/14 主分类号 H03K5/14
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