MEMORY CELL WITH A TRENCH CAPACITOR AND VERTICAL SELECTION TRANSISTOR AND ANNULAR CONTACTING AREA FORMED BETWEEN THEM

摘要

The top capacitor electrode (10) of the trench capacitor is connected to an epitactically grown source/drain area (21) of the selection transistor (20) by an annular, monocrystalline Si contacting area (7.1). The gate electrode layer (24) has an oval peripheral course around the transistor (20), wherein the oval peripheral courses of the gate electrode layers (24) form overlapping areas (24.3) of memory cells placed in rows next to one another along a word line in order to enhance packing density.