Semiconductor device with hardware mechanism for proper clock control

摘要

A semiconductor device (10) includes a clock generation unit (30) which generates a clock signal, a first module (31) which asserts a clock-control request signal (req), and one or more second modules (12, 13, 16-20), each of which receives the clock signal and the clock-control request signal (req), and asserts a clock-control acknowledge signal (ack) after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal (req), wherein the clock generation unit (30) selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules. <IMAGE>