发明名称 WIRING LAYOUT METHOD FOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make a wiring area ratio equal to or less than an allowable maximum value without depending on the way of inspection. SOLUTION: After automatic wiring, a wiring area ratio inspection is performed. A line width L is divided into three stages except the grid-shaped wiring, and a minimum space width Smin of each stage is previously specified so that the status of Lmax/(Lmax+Smin)<=Pmax can be satisfied relatively to a maximum line width Lmax of each stage. Concerning the grid-shaped wiring, the line width L of a grid is divided into two stages, an allowable minimum area Amin (Amin>=Amin0) of a metal punch area is previously specified relative to a maximum line width Lmax of the upper stage so that a wiring area ratio P can become <= the allowable maximum value Pmax and concerning the lower stage, a specification that the metal punch area A is equal to the allowable minimum value Amin0 is provided. Concerning the wiring, with which the space width or metal punch area does not satisfy the specifications in inspection, the layout thereof is corrected so that the specifications can be satisfied.
申请公布号 JP2003051539(A) 申请公布日期 2003.02.21
申请号 JP20010235677 申请日期 2001.08.03
申请人 FUJITSU LTD 发明人 DEURA MANABU
分类号 G06F17/50;H01L21/768;H01L21/82;H01L23/528;(IPC1-7):H01L21/82 主分类号 G06F17/50
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