发明名称 |
Speed of execution of a conditional subtract instruction and increasing the range of operands over which the instruction would be performed correctly |
摘要 |
A circuit which first shifts both a dividend and a divisor by an extra bit such that a 1-bit shift can be avoided after subtraction of the shifted values of dividend and the divisor, while performing a conditional subtraction instruction. The shifted divisor can conveniently replace the dividend as required for the instruction. The approach can be used to implement, among others, 2N-bit/N-bit (denoted 2N/N) division using an N-bit ALU, N/N division using N-bit ALU. The division can be implemented for all possible values of N without requiring substantially more complexity in the implementation.
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申请公布号 |
US2003037088(A1) |
申请公布日期 |
2003.02.20 |
申请号 |
US20020202151 |
申请日期 |
2002.07.24 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
GUPTE AJIT;GOVINDARAJAN SUBASH CHANDAR;TESSAROLO ALEXANDER |
分类号 |
G06F9/305;G06F5/01;G06F7/50;G06F7/52;G06F7/535;(IPC1-7):G06F7/50 |
主分类号 |
G06F9/305 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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