INTERFACE CONVERTER CIRCUIT OF SYNCHRONOUS TRANSMISSION SYSTEM

摘要

PURPOSE: An interface converter circuit of a synchronous transmission system is provided to exactly transmit data using a basic clock and a diploid number clock when transmitting data in a data bus having different transmission rates. CONSTITUTION: The first flip-flop(60) samples 8 bit basic data bus according to a reference clock. A multiplexer(61) multiplexes the 8 bit basic data bus according to an enable signal and outputs upper 4 bit and lower 4 bit data buses. The second flip-flop(62) latches the data bus from the multiplexer(61) and outputs 4 bit diploid number data bus. An enable signal generation circuit receives a frame synchronous signal and a deploid clock and generates the enable signal. The enable signal generation circuit includes the first latch for receiving the frame synchronous signal and outputting a latched signal according to a diploid number clock and the second latch for receiving an output signal of the first latch and outputting a latched signal according to a diploid number clock.