发明名称 ARITHMETIC UNIT, CENTRAL PROCESSOR AND INFORMATION PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide an arithmetic unit to enable to conduct a test by an actual clock while fluctuating input data of the arithmetic unit by using software instructions by adding simple hardware. SOLUTION: An element of immediate data to be an origin of an arithmetic operation is first set in a setting register YIR 22. An instruction register CHV 21 is tested, setting registers YIR 22, ZIR 23 perform +1 respectively. Read address registers YAR 14, ZAR 15 receive values of the setting registers YIR 22, ZIR 23 respectively. The values of the read address registers YAR 14, ZAR 15 are inputted in immediate circuits YIMM 16 and ZIMM 17 respectively. The contents of the immediate circuits YIMM 16, ZIMM 17 are inputted in YDR 41, ZDR 42. Pieces of data inputted in the YDR 41, ZDR 42 are inputted in the arithmetic unit 10 and the arithmetic operation is performed. A write register WDR 11 simultaneously holds check bits.
申请公布号 JP2003044314(A) 申请公布日期 2003.02.14
申请号 JP20010226103 申请日期 2001.07.26
申请人 NEC CORP 发明人 SHINOHARA MASASHI
分类号 G06F7/00;G06F9/30;G06F11/22 主分类号 G06F7/00
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