| 摘要 |
A semiconductor capacitance device includes a P-type semiconductor layer, an N-type well region which is provided in the P-type semiconductor layer, and a P-type well region which is provided in the N-type well region. Further, the semiconductor capacitance device includes a gate electrode layer which is provided over the P-type well region with an insulating layer interposed therebetween, a first N-type impurity layer which is provided in the P-type well region on one side of the gate electrode layer, and a second N-type impurity layer which is provided in the P-type well region on the other side of the gate electrode layer. The gate electrode layer has at least one through hole, and a third N-type impurity layer is provided in the P-type well region at a position facing the through hole.
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