| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit (LSI) in which timing design is easily performed, and any timing error is prevented when transferring data between a plurality of the LSI. SOLUTION: This semiconductor integrated circuit is provided with a first flip flop group 13 just after an input port, a second flip flop group 14 just before an output port, a third flip flop group 15 in the circuit, a first clock distributing means 16 for supplying a reference clock to the first flip flop group 13 while making almost constant the delay quantity of the reference clock signal, a second clock distributing means 17 for supplying the reference clock signal to the second flip flop group 14 while making almost constant the delay quantity of the reference clock signal, and a third clock distributing means 18 for supplying the reference clock signal to the third flip flop group 15 while making almost constant the delay quantity of the reference clock signal. In this case, the delay time of the first clock distributing means 16 is set so as to be made larger than the delay time of the third clock distributing means 18, and the delay time of the second clock distributing means 17 is set so as to be made smaller than the delay time of the third clock distributing means 18.</p> |
