发明名称 BOARD FOR CLOCK SYNCHRONIZATION TYPE BUS
摘要 <p>PROBLEM TO BE SOLVED: To perform an autonomic operation even when any bus master is not present. SOLUTION: When a bus master is present on a bus 109, a clock signal 107 is transferred as a clock signal 111, and a reset signal 108 is transferred as a reset signal 112 to an in-board circuit 113, and when any bus master is not present on the bus 109, a clock signal generated by a clock generating part 105 is transferred as the clock signal 111, and a reset signal generated by a reset generating part 104 is transferred as the result signal 112 to the in-board circuit 113 so that the autonomic operation of a board 101 can be realized.</p>
申请公布号 JP2003029866(A) 申请公布日期 2003.01.31
申请号 JP20010216247 申请日期 2001.07.17
申请人 HITACHI LTD 发明人 NAOI SHIGERU;YAMASHITA KENKICHI
分类号 G06F1/04;G06F1/10;(IPC1-7):G06F1/04 主分类号 G06F1/04
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