发明名称 |
Method and system for selecting data sampling phase for self timed interface logic |
摘要 |
An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.
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申请公布号 |
US2003023891(A1) |
申请公布日期 |
2003.01.30 |
申请号 |
US20010918081 |
申请日期 |
2001.07.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HOKE JOSEPH MICHAEL;FERRAIOLO FRANK D.;LO TIN-CHEE;YAROLIN JOHN MICHAEL |
分类号 |
H04L7/00;H04L7/033;H04L25/14;(IPC1-7):G06F1/12 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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