发明名称 METHOD OF POWER CONSUMPTION REDUCTION IN CLOCKED CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a method and device for reducing the power consumption of a clocked circuit including a plurality of latches. SOLUTION: A first latch which has more than a prescribed slack is detected within the plurality of latches. Then, the possibility of substituting an available second latch (requiring less power to operate) is determined subject to the constraint that the slack after substitution should still be positive although it may be less than the prescribed number above. When such a possibility is determined to exist, the first latch is replaced with the available second latch.</p>
申请公布号 JP2003022293(A) 申请公布日期 2003.01.24
申请号 JP20020075699 申请日期 2002.03.19
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 CHU SAM GAT-SHANG;CLABES JOACHIM GERHARD;GOULET MICHAEL NORMAND;ROSSER THOMAS EDWARD;WARNOCK JAMES DOUGLAS
分类号 G06F1/10;G06F1/12;G06F17/50;H03K3/037;(IPC1-7):G06F17/50 主分类号 G06F1/10
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