TEST CIRCUIT FOR TESTING SYNCHRONOUS MEMORY CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a test circuit for testing a synchronous memory circuit 3 which is operated with a high clock frequency and which is capable of adjusting test latency. SOLUTION: This test circuit has a frequency multiplying circuit 4 generating a high frequency clock signal for the synchronous memory chip 3 by multiplying a specific multiplication factor to the frequency of a low frequency clock from the external test unit 2, a test data generator 16 which generates test data based on a data control signal from the external test unit 2 and writes the data in the synchronous memory circuit 3, a first signal delay circuit 19 for delaying the test data by an adjustable first delay time, a second signal delay circuit 24 for delaying data from the circuit 3 to a test circuit 1 by an adjustable second delay time and a data comparing circuit 27 which compares the test data generated by the generator 16 with data from the circuit 3 and outputs a signal indicating whether the circuit 3 can operate or not to the unit 2.