Semiconductor memory device with reduced power consumption during refresh operation

摘要

A row-related control circuit is provided which changes for a normal read operation and for refresh operation the delay time from a time at which a word line is activated to a time at which a sense amplifier is activated. Even when the refresh period is made longer and the charges in a memory cell are reduced, the sensitivity of the sense amplifier is heightened so that the refresh operation becomes possible. Thus, power consumption can be reduced by prolonging the refresh intervals.