| 摘要 |
In an embodiment of this invention, a memory includes an array of memory cells, an address decoder configured to generate a decoded signal for selecting a plurality of memory cells in a memory access, an input/output block configured to transfer data corresponding to the selected memory cells into and out of the memory, a first timing circuit configured to generate a first timing signal, and a second timing circuit configured to receive the first timing signal and in response generate a strobe signal coupled to the input/output block. An interconnect line carrying the first timing signal is routed through the array so that in the memory access a time delay from when the decoded signal is generated to when the data arrives at an input terminal of the I/O block is substantially the same as a time delay from when the first timing signal is generated to when the strobe signal is generated. A memory access time is thus improved by providing tracking between time-critical signals.
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