| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device which is suitable for an SRAM memory, with which low-voltage operation and reduction of power consumption are made compatible, while securing static noise margin. SOLUTION: A voltage Vdd', higher than a power supply voltage Vdd of a peripheral circuit power line 4, is supplied from a memory cell power line 4 to a memory cell array 30 as a power supply voltage for memory cells. Therefore, since the conductance of a driving MOS transistor becomes large, the threshold of an MOS transistor inside each of memory cells can be lowered, without making the static noise margin lowered, and the ratio of the gate widths between the driving MOS transistor and a transfer MOS transistor can be set 1, so that memory cell area can be reduced. |
