发明名称 PIXEL CLOCK PLL FREQUENCY AND PHASE OPTIMIZATION IN SAMPLING OF VIDEO SIGNALS FOR HIGH QUALITY IMAGE DISPLAY
摘要 Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.
申请公布号 US2002190978(A1) 申请公布日期 2002.12.19
申请号 US19990396016 申请日期 1999.09.15
申请人 AGARWAL SANDEEP;JOHARY ARUN 发明人 AGARWAL SANDEEP;JOHARY ARUN
分类号 G09G3/20;(IPC1-7):G09G5/00 主分类号 G09G3/20
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