MULTIPROCESSOR SYSTEM AND BUS ARBITER

摘要

A system for efficient composite arbitration of equal priority of a multiprocessor bus and a split transaction comprises a shared bus, processors serving as bus masters of the shared bus, and bus slave devices serving as bus slaves of the shared bus. A bus use request to use the shared bus by a split transaction is issued by each of the processors and the bus slave devices. At least one of the bus slave devices fixedly has the highest priority of the bus use request to use the shared bus.