发明名称 |
CLOCK ADJUSTER USED IN DATA REPRODUCING DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To provide a clock phase adjuster stably adjusting the phase of a clock on the basis of the state of the change of a sampling value obtained in synchronism with the clock from reproducing signals corresponding to a prescribed pattern. SOLUTION: The clock adjuster is provided with an edge detection means detecting the edge of the reproducing signal on the basis of the state of the change of the sampling value obtained from the reproducing signal corresponding to a prescribed synchronization pattern reproduced from a recording medium, a timing signal output means outputting a timing signal at every prescribed cycle determined by the synchronization pattern from the timing of detecting the edge and a phase adjusting means adjusting the phase of the clock when the edge of the reproducing signal is detected and every time the timing signal is outputted from the timing signal output means. |
申请公布号 |
JP2002358736(A) |
申请公布日期 |
2002.12.13 |
申请号 |
JP20010165588 |
申请日期 |
2001.05.31 |
申请人 |
FUJITSU LTD;FUJITSU PERIPHERALS LTD |
发明人 |
FUKUDA KATSUHIKO;HAMADA KENICHI;TAGUCHI MASAKAZU |
分类号 |
G11B20/14;G11B7/00;G11B20/10;H03L7/08 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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