| 摘要 |
There is provided a method of displaying calculated delay which can easily grasp the state of the entire logical block and acquire the detailed information on delay violation paths. A display screen has a first window displaying a path delay list of a combination of a source and a sink of a path and a second window displaying a cell delay list of cells corresponding to the route of the path. A path is selected on the first window to display the detail of the corresponding path on the second window. It is easily possible to grasp the state of the entire logical block and acquire the detailed information on delay violation paths. The design period of a semiconductor integrated circuit can be reduced largely.
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