Instruction path coprocessor branch handling mechanism

摘要

The problem of mis-match between a program counter (14) of a CPU (10) and a byte code counter (18) of an instruction path coprocessor (IPC) (16) is addressed by causing the IPC (16) to translate IPC branch instructions to the CPU branch instructions, in which the CPU branch instructions implicitly indicate whether a corresponding IPC branch instructions should be taken and in which the CPU branch instruction will cause the CPU (10) to set its own program counter (14) to a safe location in the IPC range to avoid overflow.