| 摘要 |
A collection of testing circuits (106, 108, 110, 112) are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays (102). The combination of testing circuits can detect MRAM array defects including: open rows (209), shorted memory cells (211), memory cells which are outside of resistance specifications, and simple read/write pattern errors. The built-in test circuits include a wired-OR circuit (216, 218) connecting all the rows (206) to test for open rows (209) and shorted memory cells (211). A dynamic sense circuit (300, 400) detects whether the resistance of memory cells is within specified limits (510, 520). An exclusive-OR gate (616) combined with global write controls (612, 614, 620) is integrated into the sense amplifiers and is used to perform simple read-write pattern tests. Error data from the margin tests and the read-write tests are reported through a second wired-OR circuit (630). Outputs from the two wired-OR circuits and the associated row addresses are reported to the test processor (112) or recorded into an on-chip error status table (110). <IMAGE> |
