| 摘要 |
The present invention generally relates to a processing system and method for coalescing instruction data to efficiently detect data hazards between instructions of a computer program. In architecture, the system of the present invention utilizes a plurality of pipelines, coalescing circuitry, and hazard detection circuitry. Each of the pipelines receives and processes instructions of a computer program, and the coalescing circuitry receives a plurality of register identifiers from the pipelines. Each of the register identifiers identifies one of a plurality of registers, and the coalescing circuitry combines the plurality of register identifiers into a single register identifier such that the single register identifier identifies each of the registers identified by the register identifiers received by the coalescing circuitry. The hazard detection circuitry then compares the single register identifier with other information received by the hazard detection circuitry to detect whether a particular type of data hazard exists. Due to the combining steps of the coalescing circuitry, the number of compares by the hazard detection circuitry required to detect data hazards can be reduced, and the circuitry and complexity of implementing the hazard detection circuitry can be reduced, as well.
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