SEMICONDUCTOR INTEGRATED CIRCUIT NOT OCCURRING BUS COLLISION ON IDDQ TEST MODE

摘要

PURPOSE: A semiconductor integrated circuit not occurring a bus collision on an IDDQ test mode is provided to prevent the bus collision during the IDDQ test while not decreasing the fault coverage. CONSTITUTION: The semiconductor integrated circuit includes a plurality of transfer gates transferring an input signal to the output by responding to a control signal and a logic circuit(120). The outputs of the transferring gates are transferred to one signal line. In the IDDQ test mode, the logic circuit controls one transfer gate among the plural transfer gates to be operated by responding to the control signal and is operated by responding to an activating enable signal. The logic circuit includes an OR gate(130) operating an OR operation and outputting an operation result signal by respectively receiving the control signal for controlling one transfer gate among the plural transfer gates and the enable signal.