TEST-WRITE-IN METHOD FOR CELL ARRAY OF SEMICONDUCTOR MEMORY, AND CIRCUIT PERFORMING THE METHOD

摘要

PROBLEM TO BE SOLVED: To provide a method by which a write-in time for a cell array of a DRAM which comprises a semiconductor memory, especially, word lines and bit lines and in which a cell of a cell array is decided at an intersection point of these lines can be largely and surely shortened more than conventional one. SOLUTION: All bit lines BL in one word line WL are opened by logical combination of a column activation signal CAS and a test mode signal TM, a test data pattern is written simultaneously in all cells in the word line ML.