发明名称 METHOD AND SYSTEM FOR TESTING INTEGRATED CIRCUIT DEVICES AT THE WAFER LEVEL
摘要 PURPOSE: A method and an apparatus for electrical access and interconnection of an integrated circuit device are provided to test the device functionality efficiently and cost-effectively over the whole wafer. and to use a kerf region of the wafer as a transferring region accessing and interconnecting an input/output contact of a number of integrated circuits. CONSTITUTION: A number of integrated circuits(162,164,166,168) are formed on a semiconductor wafer in the fabrication process. A conductive trace(160,180), a conductive strap(240) and a test pad are precipitated on the unoccupied region of the wafer. These unoccupied region includes a peripheral region of the wafer and a kerf region(145,155) separating an adjacent integrated circuit device. The conductive trace forms a conductive network limited to the kerf region between adjacent integrated circuit devices. The conductive trace is interconnected by using the conductive strap, and the trace is connected to an input/output contact on the integrated circuit device. The test pad is formed on the unused peripheral region of the wafer and is connected electrically to the conductive trace network. By doing this, an on-wafer electrical test structure capable of testing the integrated circuit device before the integrated circuit device is cut from the wafer is formed.
申请公布号 SG92654(A1) 申请公布日期 2002.11.19
申请号 SG19990004662 申请日期 1999.09.17
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 SUMIT DASGUPTA;KRIS SRIKRISHNAN;RONALD GENE WALTHER
分类号 H01L27/04;G01R31/26;G01R31/27;G01R31/28;H01L21/66;H01L21/768;H01L21/82;H01L23/52;(IPC1-7):H01L21/66 主分类号 H01L27/04
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