| 摘要 |
A circuit having a data pin, an input pin for receiving a clock signal and having a zero hold time, is comprised of a sampling transistor for collecting charge at the data pin during a setup time defined by the clock signal; a device for isolating the sampling transistor from the data pin in response to the clock signal; and an output stage for outputting a logic signal in response to the charge sampled by the sampling transistor and the clock signal. The circuit may have an inverter for producing the complement of the clock signal, and the device for isolating may include a multiplexer responsive to the clock signal and the complement of the clock signal. The circuit can be operated as either a latch or a register. A method of operating a data acquisition and retention circuit having a zero hold time is also disclosed.
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