| 摘要 |
PROBLEM TO BE SOLVED: To switch a microprocessor for controlling a hardware sequencer without impairing an effective processing step. SOLUTION: This asymmetric multiprocessor is provided with a hardware sequencer HW 2 having a control register 70 mapped in an I/O space and controlled by reading/writing to the control register, a first microprocessor CPU 0 having a multistage pipeline, and readable and writable to the control register through a first I/O bus without stall, a second microprocessor CPU1 having the multistage pipeline, mounted on a position separated from the hardware sequencer, and capable of reading and writing to the control register through a second I/O bus after plural stall cycles, I/O selecting circuits 10, 12 for exclusively selecting and processing the access to the corresponding I/O bus from the first and second microprocessors, and a CPU bus 50 with memory map, to which the first and second microprocessors are connected. |
