Checkerboard parity techniques for a multi-pumped bus

摘要

Checkerboard parity techniques are disclosed. In one embodiment, a bus agent has a multi-pumped interface to generate in N elements in N phases. Each element includes N sub-elements, each sub-element being a fixed portion of an element. A parity generation circuit generates parity signals that are each a function of N sub-elements, a different sub-element from each phase.