| 摘要 |
Provided is a method for manufacturing a semiconductor device in which a MOS transistor having a reduction in a leakage current can be obtained without unnecessarily damaging an integration degree. After MOS transistor structures (4) to (10) having a first sidewall (10) are formed, an interlayer dielectric film (11) is formed over a whole surface. A silicon nitride film (12a) is deposited on the interlayer dielectric film (11). Next, trenches (31) and (32) are formed in only a memory cell region (MA) through the interlayer dielectric film (11) and a silicon nitride film (12a) such that a side-face of the sidewall (10) is exposed. A silicon nitride film (33) is deposited along internal walls of the trenches (31) and (32), and a part of the silicon nitride film (33) formed along the internal walls of the trenches (31) and (32) is then removed by etching. Thus, a sidewall (34) acting as a second sidewall is formed adjacently to the sidewall (10) in the memory cell region (MA).
|
