发明名称 LOGIC VERIFYING DEVICE WITH PATH DELAY INSPECTING FUNCTION ADDED THERETO AND LOGIC VERIFYING METHOD
摘要 PROBLEM TO BE SOLVED: To obtain a logic verifying device with a path delay inspecting function added thereto and a logic verifying method for efficiently generating a logic verification pattern only by specifying a critical path found from a timing verification result. SOLUTION: This device has a control data generation part 3 which generates event change control data (a) and generates data (b) for verification on a path, an event change control implementation part 4 which controls and implements event change processing for each signal in a circuit during logic verification according to the event change control data (a) and generates event change processing result data (c) and processing result data (d) for path analysis, a timing verification part 5 which verifies a path according to the data (b) and processing result data (d) and generates timing verification result data (e), and a logic verification result output part 6 which displays the event change processing result data (c) and the timing verification result data (e).
申请公布号 JP2002297685(A) 申请公布日期 2002.10.11
申请号 JP20010103707 申请日期 2001.04.02
申请人 MITSUBISHI ELECTRIC CORP 发明人 YOROZUI TOSHIHIRO
分类号 G01R31/3183;G01R31/28;G01R31/319;G06F17/50;(IPC1-7):G06F17/50;G01R31/318 主分类号 G01R31/3183
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