发明名称 |
Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching |
摘要 |
Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
|
申请公布号 |
US6461937(B1) |
申请公布日期 |
2002.10.08 |
申请号 |
US20000479442 |
申请日期 |
2000.01.07 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM SUNG-EUI;LEE KEUM-JOO;HWANG IN-SEAK;KOH YOUNG-SUN;AHN DONG-HO;PARK MOON-HAN;PARK TAI-SU |
分类号 |
H01L21/76;H01L21/762;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/76 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|