Semiconductor device for electrostatic discharge protection comprises transistors having multi-fingered structure, multilayer interconnections separated from one another, pad conductive layer, and contact plugs

摘要

#CMT# #/CMT# Semiconductor device for electrostatic discharge protection comprises: transistors having a multi-fingered structure; multilayer interconnections separated from one another, and formed in proportion to and connected to common drain regions of the transistors; a pad conductive layer formed on the interconnections; and contact plugs for connecting the interconnections to one another. #CMT# : #/CMT# Semiconductor device for electrostatic discharge protection comprises: transistors having a multi-fingered structure; multilayer interconnections (M1-M6) separated from one another, and formed in proportion to and connected to common drain regions of the transistors; a pad conductive layer (450) formed on the multilayer interconnections; and several contact plugs (C1-C3) for connecting interconnections of the multilayer interconnections to one another and for connecting the multilayer interconnections to the pad conductive layer so that a current flowing in the common drain regions of the transistors may pass only through the multilayer interconnections connected to the common drain regions and may flow into the pad conductive layer. #CMT#USE : #/CMT# The semiconductor device is used for electrostatic discharge protection. #CMT#ADVANTAGE : #/CMT# The inventive semiconductor device is capable of improving discharge efficiency by increasing on resistance of a metal oxide semiconductor field effect transistor having a multi-fingered structure. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The figure is a sectional view of the bonding pad structure. 450 : Pad conductive layer C1-C3 : Contact plugs L1-L3 : Interconnection layers LP1-LP3 : Interconnection patterns M1-M6 : Multilayer interconnections #CMT#ELECTRONICS : #/CMT# Preferred Device: Interconnections of each layer forming the multilayer interconnections have a stripe pattern. The multilayer interconnections include sequentially stacked first and second interconnection layers (L1-L3) comprising interconnections that are isolated island-shaped patterns (LP1-LP3) in each layer forming the multilayer interconnections, and the first and second interconnection layers are connected to the contact plugs so that current flowing the interconnections may pass through the isolated island-shaped patterns of the first and second interconnection layers and may flow into the pad conductive layer. The number of the multilayer interconnections is the same as the number of common drain regions of the transistors having the multi-fingered structure. #CMT#METALLURGY : #/CMT# Preferred Materials: The multilayer interconnections and the pad conductive layer are formed of aluminum, copper, or an alloy of aluminum and copper. Gate electrodes and source/drain regions of the transistors include silicide formed by a self-aligned silicide (SALICIDE) process. The silicide is cobalt silicide or tungsten silicide.