| 摘要 |
A semiconductor metallization processing method for multi-level electrical interconnection includes: a) providing a base insulating layer atop a semiconductor wafer; b) etching a groove pathway into the base layer; c) providing a first contact through the base layer to the area to which electrical connection is to be made; d) the groove pathway being etched and the first contact being provided in a combined manner which has the groove pathway and the first contact communicating with one another; e) providing metal within the first contact and within the groove pathway, the metal provided within the first contact and groove pathway in combination defining a first metal layer, the first metal layer having an overall thickness which is sufficient to fill the first contact and groove pathway; f) planarizing the first metal layer back to the uppermost region to form a conductive metal runner within the groove pathway; g) providing an overlying layer of insulating material which is different in composition from the base layer uppermost region; h) etching through the overlying layer selectively relative to the uppermost region to provide a second contact to the conductive metal runner which overlaps the conductive metal runner and uppermost region of insulating material of the base layer, the conductive metal runner being void of surround where the second contact overlaps the conductive metal runner; and i) depositing and patterning a second metal layer atop the etched overlying layer of insulating material.
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