| 摘要 |
PROBLEM TO BE SOLVED: To provide a parallel-to-serial converter and a parallel to serial conversion method that can reduce number of flip-flop circuits in use and ensure a timing margin furthermore for setup, and hold times at operation of logic gates. SOLUTION: The circuit for serializing parallel data comprises a first register for storing M (<N) bits that is clocked by a first clock, a second register for storing P bits of the parallel data that is clocked by a second clock which is different in phase from the first clock, a third register for storing Q bits of the parallel data (where M+P+Q=N) that is clocked by a third clock, a fourth register for storing the parallel data outputted from the third register and clocked by a 4th clock which is different in phase from the first clock, the second clock, and the third clock, and logic gates for receiving as inputs the N-bits of parallel data outputted from the first register, the second register and the fourth register to form serial data. |
