发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a technique which can prevent polishing remainder of copper, by reducing the swell of the copper in a plating growth operation in a dual-damascene process. SOLUTION: By an electrolytic plating method, a copper-plated layer is formed over the whole face of a semiconductor substrate, including the inside of a wiring groove and a connecting hole. At this time, when it is subjected to electrolytic plating so as to be divided into two or more operations, swelling of the copper generated on the wiring groove is reduced, and the polishing remainder of the copper in subsequent CMP processes is prevented.
申请公布号 JP2002270610(A) 申请公布日期 2002.09.20
申请号 JP20010070204 申请日期 2001.03.13
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 TAKADA YUJI;KAWAKAMI KAZUYA;SATO AKIRA
分类号 C25D7/12;H01L21/288;H01L21/3205;H01L21/768;(IPC1-7):H01L21/320 主分类号 C25D7/12
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