发明名称 PLL circuit and method for controlling the same
摘要 A DDS 11a divides a frequency of a reference frequency signal (f0) and supplies the frequency-divided signal to a PD 12. The PD 12 receives a phase reference signal (fr) supplied from the DDS 11a as a reference phase. On the other hand, a DDS 11b sets the signal outputted from the VCO 13 to a frequency corresponding to the frequency set in the DDS 11a, and supplies this frequency-divided signal to the PD 12. The PD 12 detects the phase difference between the aforementioned phase reference signal and the frequency-divided signal and supplies the detected phase difference to the VCO 13. The VCO 13 corrects the phase fluctuation component on the basis of the detected phase difference so as to output an output signal (fv) in which the frequency is kept constant.
申请公布号 US2002125957(A1) 申请公布日期 2002.09.12
申请号 US20010028596 申请日期 2001.12.20
申请人 TAKAHASHI MASAYUKI 发明人 TAKAHASHI MASAYUKI
分类号 H03L7/18;(IPC1-7):H03L7/00 主分类号 H03L7/18
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