发明名称 |
MEMORY ARCHITECTURE WITH CONTROLLABLE BITLINE LENGTHS |
摘要 |
A bitline architecture having bitlines with electrically controllable bitline lengths is described. The bitlines are provided with a switch which selectively couples or decouples local bitline segments of a bitline, depending on the need to execute the memory access. Bitlines with controllable bitline lengths can result in a reduction in power consumption without additional sense amplifiers or an additional metal layer.
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申请公布号 |
WO02054405(A8) |
申请公布日期 |
2002.09.06 |
申请号 |
WO2001US47378 |
申请日期 |
2001.12.04 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KIRIHATA, TOSHIAKI;MUELLER, GERHARD |
分类号 |
G11C7/12;(IPC1-7):G11C/ |
主分类号 |
G11C7/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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