A SUBSYSTEM BOOT AND PERIPHERAL DATA TRANSFER ARCHITECTURE FOR A SUBSYSTEM OF A SYSTEM-ON-CHIP
摘要
A subsystem (200) is provided at least Direct Memory Access (DMA) device (220) utilized to provide instructions to facilitate the operation of a substem processor (210). In one embodiment, a system level processor (102) initiates the provision of instructions for a subsystem (210). The DMA device may be additionally or alternatively utilized to provide data transfer capabilities to a plurality of data channels in a subsytem (200). The DMA device processes channels in a time limited manner to ensure that data is porcessed in a manner appropriate for time critical data.
申请公布号
WO02069157(A1)
申请公布日期
2002.09.06
申请号
WO2002US06331
申请日期
2002.02.28
申请人
BRECIS COMMUNICATIONS CORPORATION;GADKARI, MILEEND;GREWAL, HARSIMRAN, S.;APOSTOL, GEORGE, JR.
发明人
GADKARI, MILEEND;GREWAL, HARSIMRAN, S.;APOSTOL, GEORGE, JR.