发明名称
摘要 <p>PROBLEM TO BE SOLVED: To guarantee cell order at every unit switch in autonomously distributed manner without executing sorting for multiple routing routes by permitting each unit switch to execute switching to the output path in the growing order of time information which is written in the header of an inputted cell. SOLUTION: An ATM switch is provided with first-stage unit switches ISW#1-ISW#m respectively having m input lines and m output lines, the second- stage unit switches TSW#1-TSW#m and the third-stage unit switches OSW#1-OSW#m. The respective unit switches ISW#1-ISW#m, TSW#1-TSW#m and OSW#1-OSW#m are mutually connected. Then they refer to time information (time stamp) written in the header of the inputted cell and execute switching to the output path in the growing order of the time stamp in the time information.</p>
申请公布号 JP3319442(B2) 申请公布日期 2002.09.03
申请号 JP19990231952 申请日期 1999.08.18
申请人 发明人
分类号 H04L12/931;H04L12/28;H04L12/775;H04L12/801;H04L12/911;H04L12/937;H04L12/945;(IPC1-7):H04L12/56 主分类号 H04L12/931
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