发明名称 BIT ERROR RATE ESTIMATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a bit error rate estimating circuit capable of monitoring a low bit error rate even in a line whose use time at a low bit rate is short. SOLUTION: This circuit is provided with a phase point distribution detecting circuit 2 and an estimating circuit 3, and a phase signal constituted of nbit×nbit of received data demodulated by a digital demodulator 1 is inputted to the phase point distribution detecting circuit 2. The spread of the distribution of phase points detected near a convergence point is detected from the inputted phase signal, and the result is inputted to the estimating circuit 3. The judged result of the inputted spread of the phase points is obtained, and a bit error rate corresponding to the judged result is selected from a memory.
申请公布号 JP2002237858(A) 申请公布日期 2002.08.23
申请号 JP20010035164 申请日期 2001.02.13
申请人 NEC CORP 发明人 SASAKI TAKAHIRO
分类号 H04L27/22;H04L1/00;H04L27/00;(IPC1-7):H04L27/22 主分类号 H04L27/22
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