| 摘要 |
PROBLEM TO BE SOLVED: To provide parallel analog/digital(A/D) converter capable of power consumption reduction with a small number of clocks on an image sensor. SOLUTION: A pixel signal Vs is applied to one input terminal of a comparator 100 provided for each column, the ladder wave of a large voltage step is applied to the other input terminal by a reference voltage Vc1, a count value corresponding to the number of steps when inverting the comparator is held in a latch circuit 115 as a high-order bit, and the reference voltage Vc1 at such a time is held in a capacitor C1. Afterwards, a small voltage step is applied from a reference voltage Vc2 through C2, and a count value when inverting the comparator again is held in a latch circuit 116 for low-order bit. Thus, when high-order and low-order bits are separately quantized, the number of clocks can be reduced and the device can be composed of the circuit of low band so that power consumption can be reduced.
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